The present invention relates to a semiconductor device equipped with a protection circuit for protecting an integrated circuit block from a electrostatic discharge (ESD).
With the recent widespread use or the like of mobile devices, there has been an increasingly growing demand for a reduction in power consumption with respect to a semiconductor device. This is because the mobile devices use a rechargeable built-in battery or a dry battery or the like as a drive source or power supply. Suppressing charging and the required frequency of replacement of the dry battery low (i.e., prolonging battery life) becomes an important factor to enhance the commercial value of the mobile device.
As one factor for increasing power consumption of the semiconductor device, there exists a leak current flowing through each of transistors or diodes that constitutes an integrated circuit. The leak current is of a current that flows when the transistor or diode is in an off state or a reverse-biased state. It is desirable that in order to suppress the power consumption, each of the elements lying in the integrated circuit is so designed that the leak current is kept as small as possible.
As one method for reducing the leak current, there is known a method for suppressing a source voltage low. In a technique described in, for example, a patent document 1 (Japanese Unexamined Patent Publication No. Hei 6(1994)-5871), depressions and projections are formed in side faces of a floating gate to allow electric charges to concentrate, thus making it possible to reduce a write voltage/erase voltage of a nonvolatile memory, whereby power consumption of a memory device can be suppressed. Since, however, the number of elements of the semiconductor device is numerous, a leak current becomes a large value as the entire integrated circuit even though the value per element is negligible. Even though a leak current per element is a trillionth (1×10−12) ampere where, for example, the number of elements in the integrated circuit is a million (1×106), the sum of leak currents reaches a millionth (1×10−6) ampere. There is also a possibility that this leak current value will be innegligible depending upon the specs of the mobile device and will bring no commercial value. Thus, it is not possible to keep the leaks current small sufficiently where the source voltage is simply reduced.
On the other hand, there has been known a technique for dividing an integrated circuit into a plurality of blocks and supplying a source voltage to the driven block alone, thereby reducing a leak current. According to the technique, no leak current is generated because the undriven blocks are not supplied with the source voltage. Thus, the leak current at the entire semiconductor device can greatly be reduced.
Here, the integrated circuit includes, in many cases, the blocks which may be driven only upon the use of their corresponding functions, and the block which needs to be always driven. When the constantly driven block is contained therein, a reduction in the circuit scale of the constantly driven block where practicable is also effective in reducing power consumption.
However, a new drawback arises in that when a small-scale integrated circuit block is constituted of elements small in leak current, it becomes easy to cause an ESD damage of each element.
As the technology of preventing a transistor's ESD damage, there has been known a technique described in, for example, a patent document 2 (Japanese Unexamined Patent Publication No. Hei 9 (1997)-260504). In the technique disclosed in the patent document 2, the gate length of both end of every transistors are made longer than the gate length of its central portion to prevent electric field concentration, thereby preventing the ESD damage. However, the present technique is insufficient as the technique of preventing the ESD damage of the integrated circuit because a surge current per se cannot be reduced.
In contrast to this, there has been proposed a method of providing a protection circuit to prevent an ESD damage of each element that constitutes an integrated circuit block. FIG. 12 is a circuit diagram schematically showing a configuration of an integrated circuit having a protection circuit. As shown in FIG. 12, an internal circuit (e.g., the above constantly driven circuit) 1210 and a protection circuit 1220 are connected in parallel between a source line 1230 and a ground line 1240. While a MOS (Metal Oxide Semiconductor) transistor or a PN junction diode can be used as the protection circuit 1220, a GGNMOS (Gate Grounded NMOS) 1221 is used in the example of FIG. 12. Providing the protection circuit 1220 makes it possible to prevent an electrostatic surge.
However, a drawback arises in that when the protection circuit 1220 is provided, leak currents of elements constituting the protection circuit 1220 are generated, thereby increasing a leak current of the integrated circuit. When, for example, the protection circuit 1220 is constituted of the MOS transistor, a subthreshold current becomes a leak current. When the protection circuit 1220 is constituted of the PN junction diode, a junction leak current becomes a leak current. On the other hand, when the protection circuit 1220 is so designed that the leak current is reduced, the effect of preventing the electrostatic surge is impaired.